ASIC / SoC Design Internship

Are you passionate about revolutionizing hardware design?

Antmicro’s team of ASIC Designers is made up of innovators working on new designs and tooling for state-of-the-art silicon.

As an intern you will research and gradually contribute to R&D projects related to design, implementation and optimization of advanced Application-Specific Integrated Circuits (ASICs) for datacenters, security, IoT and other applications. Your contributions will span the entire design lifecycle, from RTL coding and synthesis to timing closure, and verification. This role offers a unique opportunity to deepen your understanding of ASIC design methodologies, including clock tree synthesis (CTS), place-and-route (P&R), and power optimization. You will be required to develop a deep understanding of digital logic and architecture. A key trait in this role is openness to new approaches and willingness to learn and gradually incorporate open source tools into your workflow.

Requirements:

• students of computer science, electronics or related fields

• availability for an intensive, 2-month summer program (ca. 300 hours in total) or for a more flexible program throughout the academic year (min. 20 hours/week, ca. 200 hours in total)

• understanding of computer architecture (RISC-V in particular)

• programming skills in HDLs (e.g. SystemVerilog, Verilog, VHDL, Chisel)

• knowledge of digital logic design, RTL, and ASIC development

• knowledge of common bus architectures like TileLink, AXI, AHB, APB, Wishbone

• knowledge of typical communication interfaces such as UART, I2C, I3C, SPI, PCIe and USB

• understanding of operating systems and low level software

• programming skills in selected compilable (C/C++, Rust) and scripting languages (Python, Bash)

• passion for open source projects

• readiness for everyday work in Linux

• ability to quickly adopt new technologies

• methodical and detail-oriented approach

• teamwork and willingness to learn from others

• good command of English